The present invention relates to fault control and restoration in a data communication system and is applicable in particular to the off-board control of multi-channel data processing boards.
Modern telecommunications systems, such as telephone exchanges, often employ a modular architecture which simplifies both maintenance and upgrading. In addition, by modularising a system the system can be made more fault tolerant, e.g. failure of one component will only result in the loss of a limited amount of processing capacity.
Considering the example of speech encoding in an exchange of a telecommunications network, multiple channels may be encoded in parallel by a single speech processing board, the board containing several Digital Signal Processors (DSPs) with each DSP having in turn several separate DSP cores capable of independently encoding respective speech signals. Thus, a board provided with eight DSPs, each having four DSP cores, may process thirty two speech channels in parallel. A given exchange may have several hundred such boards providing an extremely large overall channel capacity. The capacity may be even greater where individual processor cores are capable of handling multiple speech channels.
The task of controlling such a large number of processor boards is usually allocated to a xe2x80x9ccentralxe2x80x9d control processor which is common to all boards (referred to hereafter as the xe2x80x9coff-board controllerxe2x80x9d). The off-board controller monitors the status of the processor boards and allocates incoming speech channels accordingly. In particular, the off-board controller is notified of on-board faults so that appropriate channel termination, reallocation and restoration measures may be taken.
Each processor board is typically provided with an on-board controller which receives fault notification messages from individual DSPs on the board. These notifications include an identification of particular DSP cores identified as faulty. This information is then passed to the off-board controller where a decision is made regarding which of the processor cores should be reset. For example, an initial step may be to return an instruction to the on-board controller to reset only a DSP core notified as faulty. If the fault alarm is not cleared by this action, then the off-board controller may return a second command, identifying the DSP to which the faulty core belongs, and instructing that the entire DSP be rest. If this action still fails to clear the fault alarm, then the off-board controller may return a command to reset the entire processor board.
As has already been mentioned above, an intended advantage of a modularised architecture is to enable individual modules of a system to be upgraded without necessarily requiring the simultaneous upgrading of other system modules. However, in the case of the architecture described in the preceding paragraph, the upgrading of a processor board, e.g. to provide an increased number of channels per board, requires that the software of the off-board controller also be upgraded. If, for example, a new board is introduced in which the number of processor cores per DSP is increased from four to six, this requires a redefinition of the core groupings in the off-board controller in order that the off-board controller may issue a DSP level reset command to the correct DSP.
It is an object of the present invention to overcome or at least mitigate the above noted disadvantage of existing telecommunications systems. In particular, it is an object of the present invention to reduce the dependency of the off-board controller on the architecture of individual processor boards.
These and other objects are achieved by transferring at least part of the restoration decision responsibility from the off-board controller to the on-board controller.
According to a first aspect of the present invention there is provided a method of controlling a multi-channel processor board in a telecommunications system, the method comprising:
monitoring the fault status of a multiplicity of processor cores, each arranged to process one or more speech channels, distributed amongst a plurality of Digital Signal Processors (DSPs) of the processor board, including receiving fault alarms from fault containing DSPs at an on-board controller;
notifying an off-board controller of a received fault alarm including identifying the faulty core(s) and/or associated speech channels;
returning from the off-board controller to the on-board controller a reset command; and
identifying at the on-board controller which of the processor cores are faulty and either issuing corresponding individual core reset commands or issuing DSP reset commands to reset the DSPs to which the faulty cores belong.
Embodiments of the present invention leave the identification, if necessary, of the DSP containing a faulty core to the on-board controller. There is thus no need for the core/DSP association to be known to the off-board controller and the core grouping may be changed without necessitating any change in the software of the off-board controller.
Preferably, in response to receipt of a first reset command at the on-board controller, individual core reset commands are issued therefrom. More preferably, in response to receipt of a second reset command at the on-board controller, the DSPs to which faulty cores belong are identified and DSP reset commands issued to reset the identified DSPs.
According to a second aspect of the present invention there is provided apparatus for controlling a multi-channel processor board in a telecommunications system, the apparatus comprising:
an on-board controller arranged to monitor the fault status of a multiplicity of processor cores, each arranged to process one or more speech channels, distributed amongst a plurality of Digital Signal Processors (DSPs) of the processor board, including receiving fault alarms from fault containing DSPs at the on-board controller; and
an off-board controller arranged to receive fault alarms including an identification of the faulty core(s) and/or the associated speech channels, and to return to the on-board controller a reset command,
the on-board controller being further arranged to identify which of the processor cores are faulty and to either issue a corresponding individual core reset commands or issue DSP reset commands to reset the DSPs to which the faulty cores belong.
Preferably, the apparatus of the invention comprises a memory associated with the on-board controller and arranged to store the identity of cores from which fault alarms have been received. The memory may also be arranged to store the identity of the DSP to which a faulty core belongs.